Senior Researcher · imec · Leuven

Siva Satyendra
Sahoo

Designing adaptable computing systems for emerging technologies.

I connect semiconductor technology, computer architecture, and intelligent design methods to shape efficient, adaptable, and dependable systems.

Siva Satyendra Sahoo beside a Robert Noyce exhibit at the Intel Museum
Intel Museum · Santa Clara, California · 2013

Technology · architecture · design intelligence

Five research fields

Research in focus

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Full record ↗

Poster accepted

FASTER · Scaling effects in reconfigurable fabrics

Examines how gate-all-around (GAA) and complementary FET (CFET) technology nodes affect reconfigurable-system evaluation.

IEEE International Conference on Field-Programmable Technology (FPT)

Paper accepted

SHiFT · Heterogeneous switches for FPGA fabrics

Explores technology-aware FPGA optimization by allowing different switch structures within the same reconfigurable fabric.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Journal article accepted

AxO-ReQ · Reliable approximate neural acceleration

Designs redundancy-aware approximate multipliers for reliable acceleration of quantized neural networks.

Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · IEEE TCAD

Presented

ChiSER · Resource-aware chiplet exploration

Uses surrogate models to explore chiplet-based deep-neural-network accelerators under resource constraints.

ACM/IEEE Design Automation Conference (DAC)

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Presented

XRel-Graph · Cross-layer reliability management

Applies graph learning to coordinate reliability decisions across layers in embedded mixed-criticality systems.

ACM/IEEE Design Automation Conference (DAC)

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Five connected fields.
One systems perspective.

Each field is a doorway into the questions, methods, visuals, and publications behind the work.

Recently published works

Recent publications span approximate arithmetic, reconfigurable fabrics, chiplet exploration, and learning-guided dependability.

15Peer-reviewed journals
28Conference proceedings
4Book chapters

Recent publications · 2025–2026

View all publications ↗
[FPT '26]Conference poster

FASTER: Fabric Analysis of Semiconductor Technology Scaling Effects for Reconfigurable System Evaluation under GAA and CFET Nodes

[IEEE TCAD '26]Journal article · CASES

AxO-ReQ: Redundancy-Aware Approximate Multipliers for Reliable Quantized Neural Acceleration

[ICCAD '26]Conference paper

SHiFT: Enabling Switch Heterogeneity in Technology-aware FPGA Fabric Optimization

[DAC '26]Conference paper

ChiSER: Surrogate-Enhanced Resource-aware Exploration of Chiplet-based Deep Neural Network Accelerators

[DAC '26]Conference paper

XRel-Graph: Graph Learning-Driven Cross-Layer Reliability Management in Embedded Mixed-Criticality Systems

[IEEE ESL '25]Journal article

EMGAxO: Extending Machine Learning Hardware Generators With Approximate Operators

Curiosity first. Big picture, precise questions, real hardware.

I use top-down explanations and real-world analogies to help students connect abstract models to working systems.

TU DresdenEmbedded Hardware System Design
National University of SingaporeGraduate and teaching assistant across six modules
Research supervisionEleven projects across architecture, reliability, and embedded AI
Explore courses and supervised projects ↗

Industry perspective, academic depth.

A path through semiconductor research, AI architecture, physical design, electronic design automation, and teaching.

Logos of IISc, Samsung, imec, Intel, TU Dresden, NUS, and TCS

2023 — present

Senior Researcher

imec · Leuven, Belgium

Technology-aware architecture design and semiconductor pathfinding for next-generation computing systems.

2021 — 2022

Senior Staff Engineer · AI Computing

Samsung SAIT · Bangalore, India

Architecture modeling, design-space exploration, and workload mapping for modern AI inference engines.

2019 — 2021

Postdoctoral Researcher

TU Dresden · Dresden, Germany

Electronic-system design, AI/ML for EDA, embedded machine learning, teaching, and student supervision.

2012 — 2014

Digital Design Engineer

Intel · Bangalore, India

Physical design and design-quality assessment for dense VLSI systems-on-chip.

2008 — 2010

Assistant Systems Engineer

Tata Consultancy Services · India

Data integration, business intelligence, and performance management.

Let's exchange ideas.

For research collaborations, student supervision, invited talks, and conversations about future computing systems.