System–technology co-optimization
Workload and architecture evaluation alongside technology assumptions and implementation constraints.
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Research field 03
Technology-Aware Design
How should architecture change when devices, interconnects, memory, and 3D integration change together?
Perspective
Technology-aware design treats process technology, advanced integration, memory, and packaging as design variables—not fixed inputs. At imec, I use this perspective to connect semiconductor pathfinding with architectural choices for future computing systems.
Advanced integration
Fine-grained partitioning, chiplets, 2.5D/3D systems, and their effects on memory and communication.
Pathfinding models
Fast, interpretable models that expose useful trade-offs early in the design cycle.
Relevant publications
Selected work in this field.
Navya Agarwal, Moritz Brunion, Dawit Abdi, Chang Gao and Siva Satyendra Sahoo, FASTER: Fabric Analysis of Semiconductor Technology Scaling Effects for Reconfigurable System Evaluation under GAA and CFET Nodes. Accepted as a poster for FPT 2026.
Navya Agarwal, Moritz Brunion, Dawit Abdi, Chang Gao and Siva Satyendra Sahoo, SHiFT: Enabling Switch Heterogeneity in Technology-aware FPGA Fabric Optimization. Accepted for ICCAD 2026.
[DAC '26]Yi-Cheng Lo and Siva Satyendra Sahoo, ChiSER: Surrogate-Enhanced Resource-aware Exploration of Chiplet-based Deep Neural Network Accelerators, in Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC '26), Long Beach, CA, USA, July 26-29, 2026, doi: 10.1145/3770743.3803969.
[IEEE JXCDC '24]Sudipta Das, Bhawana Kumari, Siva Satyendra Sahoo, Yukai Chen, James Myers, Dragomir Milojevic, Dwaipayan Biswas, and Julien Ryckaert. Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 10, pp. 67-74, 2024, doi: 10.1109/JXCDC.2024.3468386.
Sahoo, Siva Satyendra, Dawit Burusie Abdi, Julien Ryckaert, James Myers, and Dwaipayan Biswas. On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. 2024 IEEE 37th International System-on-Chip Conference (SOCC ’24): 1-6.
Anita Farokhnejad, Siva Satyendra Sahoo, et al., N2 Nanosheet Pathfinding-PDK (P-PDKTM) Including Back-Side PDN 2024 IEEE European Solid-State Electronics Research Conference (ESSERC ’24), Bruges, Belgium, 2024, pp. 17-20, doi: 10.1109/ESSERC62670.2024.10719536.
[IEEE ESL '23]Y. Zhao, S. Ullah, S. S. Sahoo and A. Kumar, NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories, in IEEE Embedded Systems Letters, vol. 15, no. 4, pp. 170-173, Dec. 2023, doi: 10.1109/LES.2023.3299202.
Rai, S., Raitza, M., Sahoo, S. S., & Kumar, A. (2020). DISCERN: Distilling Standard Cells for Emerging Reconfigurable Nanotechnologies. In 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Virtual Conference and Exhibition, April 21- May 31, 2020.